The present invention relates to a semiconductor memory device, and more particularly, to a delay locked loop (DLL) circuit capable of reducing electromagnetic interference (EMI) caused by a high-frequency internal clock, thus improving the reliability of operation of a semiconductor memory device.
In a system with a variety of semiconductor devices, a semiconductor memory device serves as data storage. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into memory cells selected by addresses inputted together with the data.
As the operating speed of the system continues to increase and semiconductor integrated circuit technologies continue to advance, semiconductor memory devices are being required to input and output data at higher speeds. For the purpose of high-speed data input and output, a synchronous memory device has been developed. The synchronous memory device inputs and outputs data in synchronization with a system clock. However, because even the synchronous memory device could not meet the required data input/output speed, a double data rate (DDR) synchronous memory device was developed. The DDR synchronous memory device outputs or inputs data at falling edges and rising edges of the system clock.
The DDR synchronous memory device must process two data during one cycle of the system clock so as to input and output data at a falling edge and a rising edge of the system clock. Specifically, the DDR synchronous memory device should output data exactly in synchronization with the rising edge and the falling edge of the system clock. To this end, a data output circuit of the DDR synchronous memory device outputs data in synchronization with rising and falling edges of the system clock inputted therein.
However, the system clock is inevitably delayed until it arrives at the data output circuit because it passes through a clock input buffer, a transfer line, and so on in the semiconductor memory device. Thus, if the data output circuit outputs data in synchronization with the delayed system clock, an external device will receive data that are not synchronized with rising edges and falling edges of the system clock.
To solve this problem, the semiconductor memory device uses a delay locked loop (DLL) circuit to lock a delay of a clock signal. The DLL circuit compensates for the delay caused by internal circuits of the semiconductor memory device until the system clock inputted to the semiconductor memory device is transferred to the data output circuit. The DLL circuit finds the delay time of the system clock, which is caused by the clock input buffer, the clock transfer line, etc. of the semiconductor memory device. Then, the DLL circuit delays the system clock according to the found delay time and outputs the delayed system clock to the data output circuit. That is, the DLL circuit outputs the delay-locked system clock to the data output circuit. The data output circuit outputs data in synchronization with the delay-locked system clock. Therefore, it seems that the data are correctly outputted to the external circuit in synchronization with the system clock.
In an actual operation, the delay-locked system clock is transferred to the data output circuit at a time point earlier by one period than a time point when the data must be outputted, and the data output circuit outputs data in synchronization with the received delay-locked system clock. In this way, it seems that the data are outputted exactly in synchronization with the rising and falling edges of the system clock inputted to the semiconductor memory device. That is, the DLL circuit is a circuit to find how fast the data should be outputted in order to compensate for the delay of the system clock within the semiconductor memory device.
Recently, as the semiconductor memory device is required to operate at a high speed, a frequency of the system clock inputted to the semiconductor memory device is gradually increasing. Thus, the DLL circuit should control the phase of the system clock more precisely and prevent the system clock from being distorted by jitter. However, a lot of elements are highly integrated within the semiconductor memory device and a high frequency clock causes unintended electromagnetic interference (EMI), leading to malfunction of the elements within the semiconductor memory device.
FIG. 1 is a conceptual diagram illustrating an operation of a spread spectrum of a clock.
Specifically, FIG. 1 is a graph illustrating a power and a voltage with respect to a conventional clock in a frequency domain and a time domain, and also illustrating a power and a voltage with respect to a clock obtained by a spread spectrum in a frequency domain and a time domain. It can be seen from FIG. 1 that the degree of EMI is decreased after the spread spectrum.
The spread spectrum is a scheme that transmits information using a wider bandwidth than a theoretical bandwidth necessary to transmit the specific information. A usage efficiency of the frequency domain is low, but an error efficiency or signal-to-noise (S/N) ratio is good. Furthermore, if the frequency of the clock is correctly locked, EMI is concentrated on the corresponding frequency. This may affect peripheral devices and exceed limits recommended in the regulation of EMI. For these reasons, energy is dispersed by making the frequency of the clock changed within a predetermined range, instead of exactly locking. In this way, the problem of EMI can be solved.
Referring to FIG. 1, when the conventional clock has a single frequency, the power of the clock in the frequency domain exceeds the guideline level in respect to EMI of the Federal Communications Commission (FCC), i.e., FCC limit. When the semiconductor memory device operates at a low frequency or has a low integration density, problems caused by the EMI may be slight. However, in semiconductor memory devices recently developed, malfunction of internal elements due to the EMI may incur serious problems. Therefore, jitter components are intentionally inserted into the clock through a spread spectrum, thus making the frequency of the clock spread within a predetermined range. The predetermined range where the frequency of the clock can be spread is limited to a range where an error does not occur in inputting/outputting data corresponding to the received command and address.
FIG. 2 is a block diagram of a DLL circuit in a conventional semiconductor memory device.
Referring to FIG. 2, the DLL circuit includes an input buffer 210, first and second delay units 250A and 250B, first and second phase detectors 220A and 220B, first and second replica delay lines 270A and 270B, first and second duty cycle correction (DCC) mixers 260A and 260B, a DCC phase detector 240, a DCC controller 230, and first and second phase separators 280A and 280B. The second phase separator 2808 is not essential but optional.
The input buffer 210 receives first and second system clocks CLK and CLKB from the outside and outputs first and second internal clocks CLKIN1 and CLKIN2 to the first and second delay units 250A and 250B. The first delay unit 250A generates a rising delay clock RISING_CLK by delaying the first internal clock CLKIN1 by an amount of delay determined by a first delay update signal DELAY_UP_R outputted from the first phase detector 220A, and outputs the generated rising delay clock RISING_CLK to the first and second DCC mixers 260A and 2608. The second delay unit 250B generates a falling delay clock FALLING_CLK by delaying the second internal clock CLKIN2 by an amount of delay determined by a second delay update signal DELAY_UP_F outputted from the second phase detector 2208, and outputs the generated falling delay clock FALLING_CLK to the first and second DCC mixers 260A and 2608.
The first and second DCC mixers 260A and 260E corrects the duty cycle ratios of the rising delay clock RISING_CLK and the falling delay clock FALLING_CLK. The DCC phase detector 240 detects the phases of the rising delay clock RISING_CLK and the falling delay clock FALLING_CLK, and outputs their duty cycle ratios to the DCC controller 230. The DCC controller 230 controls the first and second DCC mixers 260A and 260B, considering weight factors for correcting the duty cycle ratios. The first and second DCC mixers 260A and 2608 correct the input clock to a duty cycle ratio of 50:50 and outputs a DCC clock DCC_OUT to the first and second phase separators 280A and 280B and the first and second replica delay lines 270A and 270B. Finally, the first phase separator 280A outputs rising and falling DLL clocks RCLKDLL and FCLKDLL respectively in synchronization with the rising and falling edges of the system clock CLK on the basis of the DCC clock DCC_OUT.
The first and second replica delay lines 270A and 270B models a time that is taken until an inputted system clock is transferred through the buffer and the clock input/output path to the data output circuit. It is usual to use replica of components existing on a clock path. Feedback clocks FB1 and FB2 outputted from the first and second replica delay lines 270A and 270B are inputted to the first and second phase detectors 220A and 220B, respectively. The first phase detector 220A compares a phase of a reference clock REF_CLK from the input buffer 210 with a phase of the feedback clock FB1 and outputs the first delay update signal DELAY_UP_R, which is used for the first delay unit 250A to determine the amount of delay of the first internal clock CLKIN1. The second phase detector 220B compares a phase of the reference clock REF_CLK from the input buffer 210 with a phase of the feedback clock FB2 and outputs the second delay update signal DELAY_UP_F, which is used for the second delay unit 250B to determine the amount of delay of the second internal clock CLKIN2.
When the first phase detector 220A detects the phase locking, it maintains the state without controlling the determined amount of delay. At this point, the second phase detector 220B stops its operation in order to reduce the power consumption. In FIG. 2, the second DCC mixer 260B and the second replica delay line 270B, which stops their operations in order to reduce the power consumption in the phase locked state, are indicated by dotted lines.
FIG. 3 is a block diagram illustrating the first delay unit 250A of FIG. 2.
Referring to FIG. 3, the first delay unit 250A receiving the first delay update signal DELAY_UP_R includes a delay improvement control unit 252, a first delay line control unit 254, a first delay line 256, a first mixer control unit 258, and a first mixing unit 259.
The delay improvement control unit 252 receives an internal periodic signal D and outputs, to the first line control unit 254, periodic signals PU_4 to PU_N whereby a period of varying an amount of delay of the first delay line 256 is determined. The first delay line control unit 254 receives the first delay update signal DELAY_UP_R and outputs delay control signals SHIFT_LEFT and SHIFT_RIGHT to the first delay line 256 according to the periodic signals PU_4 to PU_N outputted from the delay improvement control unit 252. The first delay line 256 controls the amount of delay by making the first internal clock CLKIN1 pass through a different number of unit delay elements according to the delay control signals SHIFT_LEFT and SHIFT_RIGHT. First and second internal delay clocks C0CLK and C1CLK outputted from the first delay line 256 have a phase difference corresponding to the amount of delay of the unit delay elements. Thereafter, the phases of the first and second internal delay clocks C0CLK and C1CLK are finely readjusted by the first mixing unit 259. The first mixer control unit 258 controlling the first mixing unit 259 receives the delay control signals SHIFT_LEFT and SHIFT_RIGHT from the first delay line control unit 254 and outputs fine control signals T1, T1B, T2, T2B, . . . , TN, TNB. In response to the fine control signals T1, T1B, T2, T2B, . . . , TN, TNB, the phases of the first and second internal delay clocks C0CLK and C1CLK in controlled by an Nth of the amount of delay of the unit delay elements of the first delay line 256 (where N is a natural number). The first mixing unit 259 finely adjusts the phases of the first and second internal delay clocks C0CLK and C1CLK up to 1/N unit of the amount of delay of the unit delay elements included in the first delay line 256, and outputs the rising delay clock RISING_CLK a phase of which is locked to that of the reference clock REF_CLK.
As is well known to those skilled in the art, the first delay line control unit 254 and the first delay line 256 of the first delay unit 250A are generally used in the DLL circuit of the semiconductor memory device, and thus their detailed circuit configurations will be omitted herein. The delay improvement control unit 252, the first mixer control unit 258, and the first mixing unit 259 will be described in more detail hereinafter.
FIG. 4A is a block diagram illustrating the delay improvement control unit 252 of FIG. 3.
Referring to FIG. 4A, the delay improvement control unit 252 includes a multiplexer and a plurality of flip-flops. The multiplexer transfers the internal periodic signal D in response to a control signal CTRL. The flip-flops receive an output signal of the multiplexer and output the periodic signals PU_4 to PU_N in response to the system clock CLK.
During the operation of the DLL circuit, the first phase detector 220A continues to compare a phase of the feedback clock FB1 and a phase of the reference clock REF_CLK and outputs the first delay update signal DELAY_UP_R according to the comparison result. A value of the first delay update signal DELAY_UP_R may continuously change. Accordingly, if the amount of delay of the first delay line 256 changes whenever the value of the first delay update signal DELAY_UP_R changes, power consumption may increase excessively. Furthermore, when the phase difference between the feedback clock FB1 and the reference clock REF_CLK is not great, the output of the first phase detector 220A may be inconsistent due to the change in the amount of delay of the first delay line 256. Thus, the first phase detector 220A may repetitively output contradictory results. In this case, changing the delay value of the first delay line 256 may prevent the DLL circuit from going to the phase locked state. Hence, in case that the first phase detector 220A outputs the same results during several periods of the system clock CLK, it is determined that the first delay update signal DELAY_UP_R is valid and the delay improvement control unit 252 enables the first delay line control unit 254. A reset signal RST applied to each flip-flop is activated when the DLL circuit is initialized. The reset signal RST may be activated when the mode of operation of the semiconductor memory device is changed, or a DLL operation is again performed after the phase locking.
FIG. 4B is a block diagram illustrating the first mixer control unit 258 of FIG. 3.
Referring to FIG. 4B, the first mixer control unit 258 includes a plurality of unit phase mixer control units. The unit phase mixer control units receive the delay control signals SHIFT_LEFT and SHIFT_RIGHT from the first delay line control unit 254 and respectively output the fine control signals T1 and T1B, T2 and T2B, . . . , TN and TNB for controlling unit phase mixers of the first mixing unit 259.
FIG. 4C is a circuit diagram illustrating the first mixing unit 259 of FIG. 3.
Referring to FIG. 4C, the first mixing unit 259 includes first and second phase mixers 259_1 and 259_2 each having a plurality of unit phase mixers.
The unit phase mixer is implemented with a 3-state inverter for controlling a transfer speed of an input signal in response to the fine control signal. The first phase mixer 259_1 includes N number of the unit phase mixer connected in parallel with respect to the first internal delay clock C0CLK, and the second phase mixer 259_2 includes N number of the unit phase mixer connected in parallel with respect to the second internal delay clock C1CLK. Since the N unit phase mixers connected in parallel have different signal drivability according to the fine control signals T1 and T1B, T2 and T2B, . . . , TN and TNB, they can change phase transition speed while phases of the first and second internal delay clocks C0CLK and C1CLK are changed. For example, the delay value of the first mixing unit 259 becomes minimum when the N unit phase mixers are all enabled to transfer the first internal delay clock C0CLK, and it becomes maximum when one unit phase mixer is enabled.
When M unit phase mixers in the first phase mixer 259_1 (where M is greater than 1 and less than N) are enabled, (N−M) unit phase mixers in the second phase mixer 259_2 are enabled. The signals outputted from the first and second phase mixers 259_1 and 259_2 are merged to output the rising delay clock RISING_CLK. In this way, the first mixing unit 259 can achieve the phase control up to 1/N unit of the amount of delay of the unit delay elements included in the first delay line 256.
FIG. 5 is a timing diagram illustrating the operation of the semiconductor memory device of FIG. 2.
Referring to FIG. 5, the first phase detector 220A compares the phase of the reference clock REF_CLK with the phase of the feedback clock FB1, and the second phase detector 220B compares the phase of the reference clock REF_CLK with the phase of the feedback clock FB2. The comparison results outputted from the first and second phase detectors 220A and 220B are used to control the amount of delay of the first and second delay units 250A and 250B. Referring to the first delay unit 250A as an example, the amount of delay of the first delay unit 250A is firstly controlled according to the comparison result in response to the periodic signals PU_4 to PU_N outputted from the delay improvement control unit 252. The first mixing unit 259 finely readjusts the controlled amount of delay of the first delay unit 250A. Thus, the DLL circuit of the conventional semiconductor memory device can achieve the fine phase locked state. The rising and falling DLL clocks RCLKDLL and FCLKDLL outputted from the DLL circuit become a finely-phase-controlled signal have a single frequency.
As described above, the phases of the rising and falling DLL clocks RCLKDLL and FCLKDLL outputted from the DLL circuit of the conventional semiconductor memory device can be finely controlled. As semiconductor memory devices use system clocks having high frequencies, the rising and falling DLL clocks RCLKDLL and FCLKDLL having finely controlled phases are very advantageous to controlling data output timings.
However, when the rising and falling DLL clocks RCLKDLL and FCLKDLL having the finely controlled phases are analyzed in the frequency domain, the power of the rising and falling DLL clocks RCLKDLL and FCLKDLL may exceed the FCC limit as described in FIG. 1. This may cause EMI in highly integrated semiconductor memory devices using system clocks with high frequencies, leading to malfunction of internal elements.